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? semiconductor components industries, llc, 201 7 1 publication order number: may 2017 - rev. 1.0 FAN105BM6X fan105b m6x offline primary - side - regulation (psr) quasi - resonant valley switch controller fan105b is offline primary - side - regulation (psr) pwm controller with quasi - resonant (qr) mode controller to achieved c onstant - v oltage (cv) and c onstant - c urrent (cc) c ontrol for travel adaptor (ta) requirement, and provide cost - effective , simplified circuit for energy - efficient power supplies. fan105b integrates proprietary operation of energy saving feature at no load , mwsaver technology that combines our most energy efficient process and circuit technologies for power adapter design. fan105b can be used in tra vel adapter design by stand - alone or co - work wit h secondary - side sr controller fan 62 92b . when paired fan105b with fan62 92b , both sr and usb type - c connector are compatible to achieve higher power and advanced control applications . features ? mwsaver? technology provides ultra - low standby power consumption for energy stars 5 - star level (<30 m w with hv fet ) ? constant - current (cc) and constant - voltage(cv) with primary - side regulation eliminates secondary - side feedback component ? valley switch o peration for h ighe st average e fficiency ? programmable cable drop compensation(cdc) with one external resistor ? integrated dynamic response enhance ement(dr e ) function ? low emi emissions and common mode noise ? c ycle - by - c ycle c urrent l imiting ? output short - c ircuit protection ? scondary side rectifier short detection via current sense protection(csp) ? integrated constant current compensation for precise cc regulation ? output over - voltage protection (vsovp) ? output und er - voltage protection (vs u vp) ? v dd over - voltage protec tion (v dd ovp) ? internal thermal - shutdown protection (otp) ? programmable brown - in and brown - out protection typical applications ? travel adapter for smart phones, feature phones, and tablet pcs ? ac - dc adapters for portable devices that require cv/cc control www. onsemi.com marking diagram pin connections ordering information part number operating temperature range package packing method fan105b m6x - 40 oc ~125oc 6 - lead, sot2 3 tap & reel for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specifications brochure, brd8011/d . = year code pxx = 5a0 : fan105b m6x = 5b0 : FAN105BM6X e x = die run code - - - = week code p x x e x - - - - c s g n d g a t e a u x v s v d d
? semiconductor components industries, llc, 201 7 2 publication order number: may 2017 - rev. 1.0 FAN105BM6X figure 1. fan105b typical application schematic figure 2. fan105b function block diagram v s s a m p l e / h o l d v a l l e y d e t e c t i o n d i o d e d i s c h a r g e d e t e c t i o n c o m p e n s a t o r o s c p e a k c u r r e n t d e t e c t i o n i o e s t i m a t o r i n t e r n a l r e g u l a t o r v c s - l i m v s p w m b l o c k c a b l e d r o p c o m p e n s a t i o n v d d o n / o f f t d i s 2 . 5 v v d d a u x t d i s v c s _ p k a r m o d e p r o t e c t i o n v c s _ c t r l e a v v d o c p o c p o t p c s g a t e g n d b r o w n o u t / i n v s o v p / u v p d r e d e t e c t i o n v d d o v p v d d 7 . 5 v m a x i m u m o n t i m e n o - l o a d c o n t r o l c o m i c o m v d y n l e b c u r r e n t m o n i t o r i v s s 1 v a c n p n s g a t e c s g n d a u x v d d v s f a n 1 0 5 b r s n 1 c s n 2 r c s m o s f e t d s n 1 d v d d b r i d g e c d l 1 c d l 2 c o 1 r s t a r t d e p l e t i o n m o s f e t l f u s e + - d r v b u s l p c f a n 6 2 9 2 b g a t e g n d v i n b l d / a u x c c 2 c c 1 l g a t e c c 1 c c 2 s r m o s f e t u s b t y p e - c g n d t x 1 + t x 1 - v b u s c c 1 d + d - s b u 1 v b u s r x 2 - r x 2 + g n d c c 1 c c 2 g n d t x 2 + t x 2 - v b u s c c 2 d + d - s b u 2 v b u s r x 1 - r x 1 + g n d v b u s v b u s v b u s v b u s c o 2 r l p c 1 r l p c 2 r f b o p t o - c o u p l e r o p t o - c o u p l e r r c d c n a r v s 1 r v s 2 c v s r g a t e c v d d r o t l o a d s w i t c h
? semiconductor components industries, llc, 201 7 3 publication order number: may 2017 - rev. 1.0 FAN105BM6X pin function description pin # name description 1 cs current sense . this pin connects to a current - sense resistor to detect the mosfet current for peak - current - mode control for output regulation. the current - sense information is also used to estimate the output current for cc regulation. 2 gnd ground 3 gate pwm signal output . this pin has an internal totem - pole output driver to drive the power mosfet. the gate driving voltage is internally clamped at 7.5 v. 4 vdd power supply . ic operating current and mosfet driving current are supplied through this pin . this pin is typically connected to an external v dd capacitor. 5 vs voltage sense . this pin detects the output voltage information and diode current discharge time based on the voltage of auxiliary winding. it also senses sink current through the auxilia ry winding to detect input voltage information. 6 aux auxiliary function . this pin generates one voltage level proportional to output current to compensate output voltage drop due to cable resistance. the pin is also used for startup with external hv fet .
? semiconductor components industries, llc, 201 7 4 publication order number: may 2017 - rev. 1.0 FAN105BM6X a bsolute maximum ratings (note 1 ,2,3 ,4 ) parameter symbol min. max. unit dc supply voltage v vdd - 0.3 30 v aux pin input voltage v aux - 0.3 30 v vs pin input voltage v vs - 0.3 6.0 v cs pin input voltage v cs - 0.3 6.0 v power dissipation (t a =25 ? c) p d 0.391 mw operating junction temperature t j - 40 +150 ? c storage temperature range t stg - 6 0 +150 ? c lead temperature (soldering , 10 seconds) t l +260 ? c electrostatic discharge capability human body model , ansi/esda/ jedec , jesd22_a114 esd >1.5 kv charged device model , jedec:jesd22_c101 >0 .5 1. stresses exceeding the absolute maximum ratings may damage the device. the device may not function or be operable above stressing the parts to these levels is not recommended. in addition, extended exposure to stresses above the recommended operating conditions may affect device reliability. the absolute maximum ratings are stress ratings only. 2. all voltage values, except differential voltages, are given with respect to the gnd pin. 3. stresses beyond those liste d under absolute maximum ratings may cause permanent damage to the device. 4. meets jedec standards js - 001 - 2012 and jesd 22 - c101. thermal characteristics (note 5 ) parameter symbol min. max. unit junction - to - ambient thermal impedance ja 242 c/w junction - to - top thermal impedance jt 56 c/w 5. t a =25c unless otherwise specified. recommended operating ranges (note 6 ) parameter symbol min. max. unit cs pin input voltage v cs 0 0.8 v gate pin input voltage v gate 0 8.0 v vdd pin input voltage v dd 7 .0 25 v vs pin input voltage v vs 1.6 3.2 v aux pin input voltage v aux 5.0 25 v 6. the recommended operating conditions table defines the conditions for actual device operation. recommended operating conditions are specified to ensure optimal performance. on semiconductor does not recommend exceeding them or designing to absolute maximum ratings.
? semiconductor components industries, llc, 201 7 5 publication order number: may 2017 - rev. 1.0 FAN105BM6X continues on next page electrical characteristics v dd = 12 v and t a = - 40~ 8 5 ? c unless noted parameter test conditions symbol min typ max unit v dd section turn - on threshold voltage v dd - on 16.5 17.5 18.5 v turn - off threshold voltage v dd - off 6.1 6.5 6.9 v v dd over - voltage - protection level v dd - ovp 2 6.5 2 8.0 2 9 . 5 v v dd over - voltage - protection de - bounce time t d - vdd - ovp - 120 200 s startup current (8) i dd - st - 20 a operating current i dd - op 1 1.4 1.7 ma deep green - mode operating current i dd - dpgn 375 450 525 a oscillator section maximum voltage - mode quasi - resonant blanking frequency f osc - bnk - max 70 76 82 khz minimum current - mode time - out blankig frequency f osc - bnk - min 4.5 5.0 5.5 khz deep green mode operating frequency (8) f osc - dpgn 320 420 480 hz minimum ccm prevention frequency ( 7 ) f osc - c cm - prvent 18 21 24 khz over - temperature protection section over - t emperature protection threshold ( 7 ) t otp - h 1 2 0 ? c over - t emperature protection recovery threshold ( 7 ) t otp - l 1 0 0 ? c
? semiconductor components industries, llc, 201 7 6 publication order number: may 2017 - rev. 1.0 FAN105BM6X continues on next page electrical characteristics v dd = 12 v and t a = - 40~ 8 5 ? c unless noted parameter test conditions symbol min typ max unit voltage sampling section reference voltage of constant voltage feedback v vr 2.475 2.500 2.525 v vs sampling phase - shift resistance ( 7 ) r vs - s/h 3 00 k vs sampling phase - shift capacitance ( 7 ) c vs - s/h 5 pf vs sampling blanking time of high level io o ver 100ma t vs_bnk - h 1.65 1.80 2.00 s vs sampling blanking time at cc controlling t vs_bnk - cc 2.05 2.20 2.35 s vs discharging time judgment threshold voltage ( 7 ) v vs - offset 150 200 250 mv voltage sense section temperature - independent bias current i t c 9.0 10.0 11.0 a v s pin source current threshold to enable brown - o ut i vs - b rown - out 260 310 3 6 0 a brown - out de - bounce time t d - brown - out 12 17 22 m s v s pin source current threshold to enable brown - in i vs - b rown - in 405 475 545 a brown - in de - bounce time n brown - in 3 4 5 cycle output over - voltage - protection of v s sampling threshold v vs - ovp 2.70 2.80 2.90 v output over - voltage - protection debounce cycle counts n vs - ovp 3 4 5 cycle output low level under - voltage - protection of v s sampling threshold v vs - u vp 1.50 1.60 1.70 v output under - voltage protection debounce time t vs - u vp 30 40 50 m s no - load control section deep green mode entry threshold voltage of comv ( 7 ) v comv - cv - dpgn - entry 0.4 0.5 0.6 v criteria to enter deep green mode v vs_eav_hi 2.5 50 2. 6 0 0 2. 650 v deep green mode band - band control high threshold voltage v vs - eav - h 2.5 50 v deep green mode band - band control low threshold voltage v vs - eav - l 2.5 25 v criteria to exit deep green mode v vs_eav_lo 2.425 2.450 2.475 v dynamic event trigger threshold voltage in deep green mode v vs - eav - dyn 2.375 2.400 2.425 v minimum on - time at 264vac c gate =1nf t on - min - 264vac 450 500 550 ns minimum on - time at 230vac c gate =1nf t on - min - 230vac 500 550 600 ns minimum on - time at 115vac c gate =1nf t on - min - 115vac 1 25 0 1 35 0 1 45 0 n s minimum on - time at 90vac c gate =1nf t on - min - 90vac 1 50 0 1 65 0 1 80 0 n s
? semiconductor components industries, llc, 201 7 7 publication order number: may 2017 - rev. 1.0 FAN105BM6X notes: 7. guaranteed by design. 8. t a guaranteed range at 25 ? c electrical characteristics v dd = 12 v and t a = - 40~ 8 5 ? c unless noted. parameter test conditions symbol min typ max unit current feedback section reference voltage of constant current feedback v cc r 1.19 1.2 1.21 v vcs peak value amplifying gain (7) a pk 3. 9 v/v attenuator ratio of constant current feedback loop (7) a v - cc 1/3.5 v/v current sense section current limit threshold voltage v cs - lim 0. 70 0.75 0.80 v gate output turn - off delay ( 7 ) t pd 100 ns leading - edge blanking time ( 7 ) t leb 150 200 250 ns gate section maximum on - time t on - max 15 17 20 s gate output voltage low v gate - l 0 1.5 v internal gate pmos driver on v dd - pmos - on 7.0 7.5 8.0 v internal gate pmos driver off v dd - pmos - off 9.0 9.5 10.0 v gate output clamp ing voltage vdd level higher than 9v v gate - clamp 7.0 7.5 8.0 v aux section dynamic response enhance ment (dre) function trigger threshold current at aux i d r e - det 110 140 170 a cdc compensation voltage at internal reference r cdc is 330k v vs - cdc 4 0. 298 0.32 0 0.3 43 v r cdc is 560k v vs - cdc3 0.223 0.240 0.257 v r cdc is 920k v vs - cdc2 0.149 0.160 0.171 v r cdc is 1.3m v vs - cdc1 0.074 0.080 0.086 v
? semiconductor components industries, llc, 201 7 8 publication order number: may 2017 - rev. 1.0 FAN105BM6X typical performance characteristics figure 3. turn - on threshold voltage (v dd - on ) vs. temperature figure 4. turn - off threshold voltage (v dd - off ) vs. temperature figure 5. operating supply current (i dd - op ) vs. temperature figure 6. deep green mode operation current (i dd - dpgn ) vs. temperature figure 7. maximum operation frequency of qr blanking time (f osc - bnk - max ) vs. temperature figure 8. deep green mode operation frequency (f osc - dpgn ) vs. temperature 0.94 0.96 0.98 1.00 1.02 1.04 1.06 - 40 - 30 - 15 0 25 50 75 85 100 125 v dd - on , normalized tempeature ( c) 0.991 0.994 0.997 1.000 1.003 1.006 1.009 - 40 - 30 - 15 0 25 50 75 85 100 125 v dd - off , normalized tempeature ( c) 0.94 0.96 0.98 1.00 1.02 1.04 1.06 - 40 - 30 - 15 0 25 50 75 85 100 125 i dd - op , normalized tempeature ( c) 0.7 0.8 0.9 1.0 1.1 1.2 1.3 - 40 - 30 - 15 0 25 50 75 85 100 125 i dd - dpgn , normalized tempeature ( c) 0.94 0.96 0.98 1.00 1.02 1.04 1.06 - 40 - 30 - 15 0 25 50 75 85 100 125 f osc - bnk - max , normalized tempeature ( c) 0.94 0.96 0.98 1.00 1.02 1.04 1.06 - 40 - 30 - 15 0 25 50 75 85 100 125 f osc - dpgn , normalized tempeature ( c)
? semiconductor components industries, llc, 201 7 9 publication order number: may 2017 - rev. 1.0 FAN105BM6X typical performance characteristics figure 9. reference voltage of cv feedback (v vr ) vs. temperature figure 10. vs sampling blanking time (t vs - bnk - h ) vs. temperature figure 11. output over - voltage protection of vs sampling threshold(v vs - ovp ) vs. temperature figure 12. output under - voltage of vs sampling threshold(v vs - uvp ) vs. temperature figure 13. current limit threshold voltage(v cs - lim ) vs. temperature figure 14. minmum gate turn on time(t on - min - 264 vac ) vs. temperature 0.991 0.994 0.997 1.000 1.003 1.006 1.009 - 40 - 30 - 15 0 25 50 75 85 100 125 v dd - off , normalized tempeature ( c) 0.991 0.994 0.997 1.000 1.003 1.006 1.009 - 40 - 30 - 15 0 25 50 75 85 100 125 t vs - bnk - h , normalized tempeature ( c) 0.991 0.994 0.997 1.000 1.003 1.006 1.009 - 40 - 30 - 15 0 25 50 75 85 100 125 v vs - ovp , normalized tempeature ( c) 0.940 0.960 0.980 1.000 1.020 1.040 1.060 - 40 - 30 - 15 0 25 50 75 85 100 125 v vs - uvp , normalized tempeature ( c) 0.991 0.994 0.997 1.000 1.003 1.006 1.009 - 40 - 30 - 15 0 25 50 75 85 100 125 v cs - lim , normalized tempeature ( c) 0.94 0.96 0.98 1.00 1.02 1.04 1.06 - 40 - 30 - 15 0 25 50 75 85 100 125 t on - min - 264vac , normalized tempeature ( c)
FAN105BM6X ? semiconductor components industries, llc, 201 7 10 publication order number: may 2017 - rev. 1.0 FAN105BM6X typical performance characteristics figure 15. maximum gate turn on time (t on - max ) vs. temperature figure 16. dynamic trigger current threshold (i ztc ) vs. temperature figure 17. cable compensation level 4 reference voltage(v vs - cdc 4 ) vs. temperature figure 18. brown in threshold current (i vs - brown - in ) vs. temperature figure 19. clamp voltage (v gate - clamp ) vs. temperature figure 20. brown out threshold current (i vs - brown - out ) vs. temperature 0.94 0.96 0.98 1.00 1.02 1.04 1.06 - 40 - 30 - 15 0 25 50 75 85 100 125 t on - max , normalized tempeature ( c) 0.991 0.994 0.997 1.000 1.003 1.006 1.009 - 40 - 30 - 15 0 25 50 75 85 100 125 i ztc , normalized tempeature ( c) 0.94 0.96 0.98 1.00 1.02 1.04 1.06 - 40 - 30 - 15 0 25 50 75 85 100 125 v vscdc4 , normalized tempeature ( c) 0.991 0.994 0.997 1.000 1.003 1.006 1.009 - 40 - 30 - 15 0 25 50 75 85 100 125 i vs - brown - in , normalized tempeature ( c) 0.94 0.96 0.98 1.00 1.02 1.04 1.06 - 40 - 30 - 15 0 25 50 75 85 100 125 v gate - clamp , normalized tempeature ( c) 0.94 0.96 0.98 1.00 1.02 1.04 1.06 - 40 - 30 - 15 0 25 50 75 85 100 125 i vs - brown - out , normalized tempeature ( c)
FAN105BM6X ? semiconductor components industries, llc, 201 7 11 publication order number: may 2017 - rev. 1.0 FAN105BM6X typical performance characteristics figure 21. blanking time of vsuvp ( t vs - uvp ) vs. temperature figure 22. vdd over voltage protection threshold ( v dd - ovp ) vs. temperature 0.940 0.960 0.980 1.000 1.020 1.040 1.060 - 40 - 30 - 15 0 25 50 75 85 100 125 t vs - uvp , normalized tempeature ( c) 0.94 0.96 0.98 1.00 1.02 1.04 1.06 - 40 - 30 - 15 0 25 50 75 85 100 125 v dd - ovp , normalized tempeature ( c)
FAN105BM6X ? semiconductor components industries, llc, 201 7 12 publication order number: may 2017 - rev. 1.0 FAN105BM6X functional description fan105b is an offline pwm and primary - side regulated (psr) fly - back con troller that can simplify feedback circuit and secondary side circuit compare to traditional fly - back converter. in addition, fan105b detects quasi - resonant valley switching to minimize the switching loss and get better emi perf ormance. fan105b modulate s p ulse width and switching f requency base d on feedback signal auxiliary winding signal ( vs ) and current sense signal ( cs ) . extremely a ccurately constant v oltage (cv) with cable drop compensation (cdc) and c onstant c urrent (cc) could meet strict requirement from market. the cv and cc output characteristic is shown as figure 23 . there are 4 levels (80mv - 32 0mv) choice s in cdc compensation weighting that is eas ily set via external smd resistor. figure 23. cv with cdc and cc v/i curve at the cable end fan105b implement s d ee p g ree n m ode (dpgn) with lowest switching frequency, limite s ic current c onsumption (450a) for excellent system standby power performance. furthermore, the system design allowe s two kind s of startup circuit with resistor or high voltage fet. p rotection s are : over/under voltage protection (vsovp, vsuvp), brown in and brown out , cycle by cycle over current protection(ocp), current sense resistor short protection, secondary rectifier short protection. basic cv/cc control principle figure 24 show s the circuit diagram of a psr f ly - back converter , fan105b estimate s output current through primary side peak current from cs, o u tput v oltage via a uxiliary winding signal that prop ortional to secondary side voltage, the current and voltage sampling are s hown in figure 25 . generally, discontinuous conduction mode (dcm) with valley swi tch ing operation is preferred for psr since it allows better output regulation. the operation principles of dcm/bcm flyback converter are as follows: during the mosfet turn on time ( t on ), input voltage (v dl ) is applied across the primary - side inductor (l m ). then mosfet current (i ds ) increases linearly from zero to the peak value (i pk ). meanwhile , the energy is drawn from the input and stored in the inductor. when the mosfet is turned off, the energy stored in the inductor forces the secondary diode (d sec ) to turn on. while the diode is conducting, the output voltage (v o ), together with diode forward voltage drop (v f ), are applied across the secondary - side inductor ( l m ? n s 2 / n p 2 ) and the diode current (i d ) decreases linearly from the peak value (i pk ? n p /n s ) t o zero. at the end of inductor current discharge time ( t dis ), all the energy stored in the inductor has been delivered to the output. when the diode current reaches zero, the transformer auxiliary winding voltage (v aux ) begins to oscillate by the resonanc e between the primary - side inductor (l m ) and the effective capacitor loaded across mosfet. during the inductor current discharge time, the sum of output voltage and diode forward - voltage drop is reflected to the auxiliary winding side as (v o +v f ) ? n aux /n s . since the diode forward - voltage drop decreases as current decreases, the auxiliary winding voltage reflects the output voltage best at the end of diode conduction time, where the diode current diminishes to zero. by sampling the winding voltage at the en d of the diode conduction time, the output voltage information can be obtained. the internal error amplifier for output voltage regulation (eav) compares the sampled voltage with internal precise reference to generate error voltage (comv), which determines the duty cycle of the mosfet in cv mode. t he output current is obtained by averaging the triangular output diode current area over a switching cycle as: ( 1 ) the intern al fan105b circuits identify the peak value of the drain current with a peak detection circuit and calculate the output current using the inductor discharge time (t d is ) and switching period (t s ). this output information (eai) is compared with internal precise reference to generate error voltage (comi), which determines the duty cycle of the mosfet in cc mode. with truecurrent? technique, constant output cu rrent can be precisely controlled. with a given current sensing resistor, the output current can be programmed as: ( 2 ) of the two error voltages, comv and comi, the smaller one determines the duty cycle. during constant voltage regulation, comv determines the duty cycle while comi is saturated to high . during constant current regulation, comi determines the duty cycle whil e comv is saturated to high . o 1 i 2 dis p d avg pk ss t n ii nt ?? ? ? ? ? ? v o i o m a x i m u m s p e c i f i c a t i o n b e f o r e c a b l e c o m p e n s a t i o n m i n i m u m s p e c i f i c a t i o n a f t e r c a b l e c o m p e n s a t i o n
FAN105BM6X ? semiconductor components industries, llc, 201 7 13 publication order number: may 2017 - rev. 1.0 FAN105BM6X figure 24. simplified psr flyback converter circuit figure 25. cycling current and v s s ampling in dcm quasi - resonant valley switch fan105b build - in quasi - resonant valley detecting function and inductor discharging time detecting function. du ri ng mosfet turn off period, fan105b che c ked falling of vvs, tdis information will update as falling of vvs checked. fan105b keep monitor both vvs and ivs after tdis checked. fan105b maximum period of mosfet on time and off time could be reach 45s, it was depending on whether valley checked. quasi - resonant valley switching could minimize mosfet switching loss during switch on , meanwhile, to eliminate emi and common mode switching component noise. charger system would be getting better efficiency than non - valley switch ing methodology. output voltage sampling vs voltage which is reflect ed auxiliary winding and proportional to output voltage. therefore, it is possible to regulate output voltage by sensing vs voltage . figure 26 show n vs sampling waveform with secondary rectifier that using schottky dio de or synchronous rectifier (sr). in order to regulate output voltage in accurately range, fan105b build - in vs sampling methodology for signal like figure 26 showed, fan105b sample s and hold vs voltage as eav at timing like gray point showed . base on eav level to regulate pulse width to achieve estimat ion output voltage . figure 26. v s sampling with diode or s ynchronous rectifier a leading edge blanking time(t vs - bnk - h/l ) start from primary switch turned off. most of ta design have vs oscillation after primary switch turned off, that is caused by the resonance of leakage inductance and parasistic capacitance at transformer . in order to avoid vs sampling procedure get impact ed by that ringing , t he oscillation should be settle before settle down before t vs - bnk - l ended as figure 26 showed . t dis is secondary rectifier current discharging time which recommend better design is longer than t vs - bnk - h during miimum on time controlling . t dis i s predict able by following formula: ( 3 ) w here parameter : t off - delay is switch turn off delay time that level is chaging in differences system criteria, t on - min is minimum turn on time in design that should consider propagation delay from ic gate to switch gate. o utput voltage can be describe by be l ow equation: ( 4 ) deep green mode (dpgn) operation in cv mode fan105b integrated mwsaver? technology that minimize current consumption and frequency at dpgn mode is fixed to minimum switching frequency ( f osc - dpgn ) and variable pulse width base d on v s sampling voltage (eav). + - c c e s t i m a t o r p w m c o n t r o l b l o c k v d l r s n 1 c s n 1 d s n 1 r c s m o s f e t n p c o d s e c v o c v e s t i m a t o r n s n a r g a t e r c g e a v e a i v v r c o m i c o m v g a t e c s c s v s r v s 1 r v s 2 c v s v a u x c d l v c c r i d s ( m o s f e t d r a i n - t o - s o u r c e c u r r e n t ) t d i s t o n t s i d ( d i o d e c u r r e n t ) v s ( w i t h s c h o t t k y ) p pk s n i n ? pk i o d avg ii ?? ? 2 12 vs a f s vs vs r n v n r r ?? ? 2 12 vs a o s vs vs r n v eav n r r ? ? ? ? t o n v a u x i l i a r y g a t e t s t d i s v s ( w i t h s r c o n t r o l ) 2 0 0 m v v s ( w i t h s c h o t t k y ) t v s - b n k - l blk p a v n n ?
FAN105BM6X ? semiconductor components industries, llc, 201 7 14 publication order number: may 2017 - rev. 1.0 FAN105BM6X v vs regulated boundary are between v vs - eav - h and v vs - eav - l . after exit dpgn, internal regulation reference voltage was changed to v vr . fan105b dpgn entry and exit criteria showed as below: ? dpgn e ntry n eed to m eet b oth c riteria as below : ? minimum frequency (f osc - min ) operation continues over than n dpgn - entry switching cycles. ? eav > v vs - eav - h (2.55 0 v) . ? dpgn e xit c riteria , meet one of below criteria : ? eav < v vs - eav - l (2.5 25 v) and maximum on time at dpgn . ? eav < v vs - eav - dyn (2.4v) . during the dpgn mode controlling, fan105b decreases the operating current down to 450a. therefore, the standby power could meet international standard requirement when work with flexible start up circuit , designer have flexible start up circuit that hv fet or start up resistor depending on cost and better standby power consideration cable drop compensation (cdc) fan105b integrate s cabl e drop compensation function and the compensation weighting is calculated based on t dis , current sense voltage (v cs ), and cdc setting resistor (r cdc ) needed to between vdd and aux pin . during start u p, as vdd reached v dd - on , cdc programming block detect s aux pin current and determine cable drop compensation weighting based on current weighting of aux pin. o nce finished cdc compensation weighting detecting , the information will stored until shu n t - down by protections or vdd lower than v dd - off . the cdc weighting automatic detected input current during start up . which provides a constant output voltage at the end of the cable over the entire load range in cv mode. the table show s the compensation weighting with corresponding r cdc setting as below : ta d esigner can eas il y to set up cdc weighting via choose r cdc following above table. in the table, resisance of r cdc is recommended for corresponding compensation level. cable drop compensation voltage at output is proportional to v vs compensation weighting that is internal referce voltage for cdc compensation. programmable brown in/ brown out fan105b implement brown out and brown i n through high side resistor setting at vs pin . in actual system operation , v s pin is drain a current (i vs ) that proportional to line voltage during mosfet turns on. i vs could predict by below equation: ( 5 ) operating current the operating current in fan105b is as small as 1.4 ma. the small operating current results in higher efficiency and reduces the v dd hold - up capacitance re q uirement. during dpgn mode , the fan105b consumption current is reduced to 45 0 a, assisting the power supply meet standby power standard requirements. protections the fan105b self - protection includes v dd over - voltage - protection (v dd ovp), internal chip over - temperature - protection (otp), vs over - voltage protection (vsovp) , vs under - voltage protection (vs u vp) , cs pin p rotection (csp) , b rownout and brown in protection, and all of protection are implemented as auto restart(ar) m ode. when when an auto - restart mode protection is triggered , switching is terminated and the mosfet remains off, causing v dd to drop till v dd - off and shut - down the system then all protections are reset . after then v dd will be charged again by the input ac voltage and once touch v dd - on then switching resumes. this is the reason why it is called auto - restart, resumes switching automatically. v dd over - voltage - protection(v dd ovp) when v dd is raised up to higher level by some reasons, transformer v dd winding turns are too many, load regulation is not good between transformer winding, vs information is not available anyhow and so on, and touches v dd - ovp , then fan105b stops switching and prot ects ic from higher v dd voltage. this is different then output voltage is over than pre determined level. vs under - voltage protection (vs u vp) fan105b bulid - in vsuvp function that prevent ta keep deliver power to phone side when output voltage is under the set voltage at vs pin. vsuvp has a 40ms de - bounce time and once vdd touches v dd - on , during the later 40ms vsuvp is disabled because vsuvp should not be triggered during the start up. vsuvp level can be calculated as below: ( 6 ) vs over - voltage protection (vsovp) t he vsovp is design ed to prevent ta output voltage is over then the rating of used component s, like capacitor . vsovp has 4 s witching cycles of denounce time and that prevent mis - triggered of vsovp by switching noise. t he protection level is changed in proportional to the cdc cdc weighting and r cdc setting r cdc label v vs compensation weighting 1.3m vs - cdc1 0.08v 920k vs - cdc2 0.16v 560k vs - cdc3 0.24v 330k vs - cdc4 0.32v
FAN105BM6X ? semiconductor components industries, llc, 201 7 15 publication order number: may 2017 - rev. 1.0 FAN105BM6X weighting. vsovp trigger level can be illustrates as following formula : ( 7 ) cs pin p rotection (csp) in order to prevent mosfet current over than safe operating area, fan105b build - in cycle by cy c le over current protection. the protection could protect mosfet damage d by saturation current and cs pin sensing error. as cs pin signal meet below conditions fan105b will turn o ff gate immediately . current sensing protectio n (csp) cr iteria shows as below : ? v cs <0.2v after switching turn on 4.5us at low line or 1.5us at high line . ? v cs >1.5v over - temperature protection(otp) in order to guarantee fan105b works within recommended temperature. fan105b build - in chip over - temperature C protection (otp). as chip junction temperature over thareshold t otp - h ic immediately terminated gate switching signal untill chip junction termperature recover to t otp - l . start up function with aux fan105b support s high voltage start up with hv fet that can make better standby power and shorter start up time. figure 27 show s start up controlling function block. figure 28 show s start up relative signa l sequence with aux controlling. a t system power on moment, initial vdd voltage is zero, internal pmos switch is turn on and external hv fet also turn on, c vdd is charged through hv fet till vdd reach v dd - on . while internal pmos switch s1 turn off and vgs of hv fet will close to internal clamping voltage (v aux - cl ) which less than hv fet vgs turn on threshold. meanwhile vdd energy supplement is turn to auxiliary winding. the voltage gap between vdd and vaux is keep at 5v till controller shut - down by protection or vdd touching v dd - off . figure 27. internal function for start up of aux pin figure 28. start up sequence with aux controlling dynamic response enhancement (dre) with aux psr flyback converter regulates output voltage within requirement specification through detects vs signal which proportional to output voltage, however vs signal can only detects when system switched. in order to get better standby power performance , the switching fr equency is decreases to quite low frequency, it can not maintaining out voltage as load suddenly increases from extremely light load to heavy load during minimum frequency operation. therefore, fan105b build in a dynamic response enhancement (dre) functio n to detects output voltage dropping immediately when fan105b pair with fan6292b. figure 29 shows dre function block . figure 30 shows dre function relative signal working sequence . w hen output voltage undershoot is acknowledged via fan6292b vin pin, bld/aux pin pull - down current via s2 switch to inform undershoot to fan105b via a photo - coupler . once fan105b sensed aux current higher than i dre - det , the switching frequency is increases immediately. figure 29. internal function for start up of aux pin v d d a u x c v d d v a u x - c l v d l v d d - o n / v d d - o f f v o d r o p d e t e c t i o n r s t a r t s 1 v d d - v a u x v d d v g a t e , s 1 v d d - o f f v d d - o n v d d - o v p v a u x - c l o p t o - c o u p l e r c o 1 c o 2 n s s r g a t e n p l g a t e v b u s r b l d / a u x f a n 6 2 9 2 b v i n v i n - a u x p u l s e s 2 r o p t o ( 3 . 3 k ) a u x r a u x r c d c v d d f a n 1 0 5 b t d i s t o n n o l o a d c o n t r o l l e a v e b a n g - b a n g c o n t r o l 1 v i a u x
FAN105BM6X ? semiconductor components industries, llc, 201 7 16 publication order number: may 2017 - rev. 1.0 FAN105BM6X figure 30. dre function detecting sequency accurately constant current (cc) compensation fan105b provide s accurate constant current with universal line voltage range, in order to achieve this accurately output current regulated, fan105b build in circuits that compensate a dc level at cs signal based on difference line voltage . it could avoid output current gap of difference line voltage during constand current controlling . for noise immunity, the recommendation of cs pin series resistor is 10. v g a t e ( f a n 1 0 5 b ) i a u x s 2 t a u x - o n i o v b u s v i n - a u x i d r e - d e t t o p t o - d e l a y h e a v y l o a d
notes: a. this package conforms to jedec mo-178, variation ab. b. all dimensions are in millimeters. c. does not include mold flash, protrusions or gate burrs. d. does not include interlead flash or protrusions. e. dimensions and tolerancing as per asme y14.5m-1994 f. drawing file name: ma06erev2 1.30 0.90 0.15 0.05 8 0 seating plane 0.60 ref 0.60 0.30 formerly: scale: 2:1 detail a approvals 5 july 07 date 2 mkt-ma06e sheet : n/a of 1 1 1.6mm wide mo-178 variation ab, 6ld,sot23,jedec see detail a gage plane 0.25 1.45 max 0.08 0.22 land pattern recommendation release to document control description symm ltr a c l revisions e.c.n. date by/app'd c c 0.10 1:1 na / 0.15 c a-b 0.15 c 2x 2x 3 tips 6x 2.9 1.6 2x 1.9 a 2.8 1.4 0.15 c d 0.95 b 2x 0.3-0.5 0.20 c a-b d d pin 1 index area (0.95) (0.95) (1.00min) (1.90) (2.60) (0.70min) r0.10min r0.10min c d d c 11/4/2006 h.allen 2 dwg updated to conform to mo178 5 july 07 l.huebener l.huebener h.allen 17 july 07
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